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RDTSC           Read Time-Stamp Counter              Flags: Not altered

RDTSC                                                CPU: Pentium+ r

        Logic   if (CR4.TSD = 0) or ((CR4.TSD = 1) and (CPL = 0))
                   EDX:EAX . TimeStampCounter
                else
                   #GP(0)
                endif

    Loads the current value of the processor's time-stamp counter into
    the EDX:EAX registers. The time-stamp counter is contained in a
    64-bit MSR. The high-order 32 bits of the MSR are loaded into the
    EDX register, and the low-order 32 bits are loaded into the EAX
    register. The processor increments the time-stamp counter MSR every
    clock cycle and resets it to 0 whenever the processor is reset.

    The time stamp disable (TSD) flag in register CR4 restricts the use
    of the RDTSC instruction. When the TSD flag is clear, the RDTSC
    instruction can be executed at any privilege level; when the flag is
    set, the instruction can only be executed at privilege level 0. The
    time-stamp counter can also be read with the RDMSR instruction.

    The RDTSC instruction is not serializing instruction. Thus, it does
    not necessarily wait until all previous instructions have been
    executed before reading the counter. Similarly, subsequent
    instructions may begin execution before the read operation is
    performed.


    Protected Mode Exceptions
    #GP(0) If the TSD flag in register CR4 is set and the CPL is greater
    than 0.

    Real Address Mode Exceptions
    #GP If the TSD flag in register CR4 is set.

    Virtual 8086 Mode Exceptions
    #GP(0) If the TSD flag in register CR4 is set.


    Opcode      Format
    0F 31       RDTSC


    Length and timing
    Operands    Bytes   8088    186     286     386     486     Pentium
    -           2       -       -       -       -       -       ??