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        Port 3C5, 00  -  Reset Register (00)

               1111 11xx  Reserved
               xxxx xx1x  Synchronous reset
                            When set to 0, this bit commands the
                            sequencer to synchronously clear and halt.
                            To prevent loss of data, bit 1 must be set to
                            0 during the active display interval before
                            changing the clock selection. The clock is
                            changed through the Clocking Mode register or
                            the Miscellaneous Output register
                            (3C2/3CC).
               xxxx xxx1  Asynchronous reset
                            When set to 0, this bit commands the sequencer
                            to asynchronously clear and halt. Resetting
                            the sequencer with this bit can cause loss
                            of video data.