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SYNTAX      DIRECT    [<LABEL>] EXAMPLE <dma>[,shift]
            INDIRECT  [<LABEL>] EXAMPLE {ind}[,shift[,<next ARP>]]
            IMMEDIATE [<LABEL>] EXAMPLE [<constant>]

            Each instruction begins with an assembler syntax expression.
            The optional comment field that concludes the syntax is not
            included in the syntax expression. Space(s) are required
            between each field (label, command, operand and comment
            fields) as shown in the syntax. The syntax example illustrates
            both direct and indirect addressing, as well as immediate
            addressing in which the operand field includes <constant>.

            The indirect addressing operand options, including bit-
            reversed (BR) addressing, are as follows:

                  TMS32020:   {*|*+|*-|*0+|*0-}

                  TMS320C25:  {*|*+|*-|*0+|*0-|*BR0+|*BR0-}


OPERANDS    0 . dma . 127; 0 . next ARP . 7; 0 . constant . 255.

            Operands may be constants or assembly-time expressions
            referring to memory, I/O and register addresses, pointers,
            shift counts, and a variety of constants. The operand values
            used in the example syntaxare shown. Note that the next ARP
            on the TMS32020 is . 4 for auxiliary registers AR0-AR4.

EXECUTION   (PC) + 1 . PC
            (ACC) + [(dma) * 2 ^ shift] . ACC
            If SXM = 1, then (dma) is sign-extended.
            If SXM = 0, then (dma) is not sign-extended.
            Affects OV; affected by OVM and SXM.
            Affects C (TMS320C25).

            An example of the instruction operation sequence is provided,
            describing the processing that takes place when the
            instruction is executed. Conditional effects of status
            register specified modes are also given. Those bits in the
            TMS320C2x status registers affected by the instruction are
            also listed.

DESCRIPTION Instruction execution and its effect on the rest of the
            processor or memory contents are described. Any constraints
            on the operands imposed by the processor or the assembler are
            discussed. The desciption parallels and supplements the
            information given by the execution block.

WORDS       1

            The digit specifies the number of memory words required to
            store the instruction and its extension words.

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  0  0  0|   shift   | 0| data memory address | DIRECT
            +-----------------------------------------------+

            15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  0  0  0|   shift   | 1| see indirect fields | INDIRECT
            +-----------------------------------------------+

            15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |1  0  0|             13-bit constant           | IMMEDIATE
            +-----------------------------------------------+

            Opcode eamples are shown of both direct and indirect
            addressing or of the use of an immediate operand.

CYCLES

            +------------------------------------------------+
            |    Cycle Timings for a Single Instruction      |
            |------------------------------------------------|
            | PI/DI | PI/DE | PE/DI | PE/DE  | PR/DI | PR/DE |
            |-------+-------+-------+--------+-------+-------|
      '20   |   1   |   1   |  1+p  |  1+p   |   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   1   |   1   |  1+p  |  1+p   |   1   |   1   |
            |------------------------------------------------|
            |    Cycle Timings for a Repeat Instruction      |
            |------------------------------------------------|
      '20   |   n   |   n   |  n+p  |  n+p   |   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   n   |   n   |  n+p  |  n+p   |   n   |   n   |
            +------------------------------------------------+

            The table shows the number of cycles reqired for a given
            TMS320C2x instruction to execute in a given memory
            configuration when executed as a single instruction or in the
            repeat mode. The column headings in the table indicate the
            program source location (PI, PE, or PR) and data destination
            or source (DI or DE) defined as follows:

                  PI    The instruction executes from internal program
                        memory (RAM).
                  PR    The instruction executes from internal program
                        memory (ROM).
                  PE    The instruction executes from external program
                        memory.
                  DI    The instruction executes using internal data
                        memory.
                  DE    The instruction executes using external data
                        memory.

            The number of cycles required for each instruction is given
            in terms of the program/data memory and I/O access times as
            defined in the following listing:

            p     Program memory wait states. Represents the number of
                  clock cycles the device waits for external program
                  memory to respond to an access. T(ac) is the access time
                  in nanoseconds, (maximum) required by the TMS320C2x for
                  an external memory access to be made with no wait
                  states. T(mem) is the memory device access time and T(p)
                  is the clock period (4/crystal frequency).

                   p = 0; If T(mem) . T(ac)
                   p = 1; If T(ac) < T(mem) . (T(p) + T(ac))
                   p = 2; If (T(p) + T(ac)) < T(mem) . (T(p) * 2 + T(ac))
                   p = k; If (T(p)*(k-1)+T(ac)) < T(mem) . (T(p)*k+T(ac))

            d     Data memory wait states. Represents the number of cycles
                  the device must wait for external data memory to respond
                  to an access. This number is calculated in the same
                  manner as the p number.

            i     I/O memory wait states. Represents the number of cycles
                  the device must wait for an external I/O memory to
                  respond to an access. This number is calculated in the
                  same manner as the p number.

            Other abbreviations used in the tables and their meanings are
            as follows:

            br    Branch from...
            int   Internal program memory.
            INT   Interrupt.
            ext   External program memory.
            n     The number of times a repeat instruction is executed
                  when using the RPT or RPTK instructions.

            See also "instruction cycle timings".



EXAMPLE     ADD   DAT1,3      (DP = 10)
            or
            ADD   *,3         If current auxiliary register contains 1281.

               BEFORE              AFTER

            dm1281 >8         dm1281  >8
             ACC X >2          ACC 0 >42
                 C                 C

            The sample code presented in the above format shows the effect
            of the code on memory and/or registers. The use of the carry
            bit (C) provided on the TMS320C25 is also shown.