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SYNTAX      DIRECT   [<LABEL>] LST <dma>
            INDIRECT [<LABEL>] LST {ind}[,<next ARP>]

OPERANDS    0 . dma . 127; 0 . next ARP . 7.

EXECUTION   (PC) + 1 . PC
            (dma) . status register ST0
            Affects ARP, OV, OVM, AND DP.
            Does not affect INTM or ARB.

DESCRIPTION Status register ST0 is loaded with the addressed data memory
            value. Note that the INTM (interrupt mode) bit is unaffected
            by LST. ARB is also unaffected even though a new ARP is
            loaded. If a next ARP value is specified via the indirect
            addressing mode, the specified value is ignored. Instead, ARP
            is loaded with the value contained within the addressed data
            memory word.

            The LST instruction is used to load status register ST0 after
            interrupts and subroutine calls. The ST0 contains the status
            bits: OV (overflow flag) bit, OVM (overflow mode) bit, INTM
            (interrupt mode) bit, ARP (auxiliary register pointer), and
            DP (data memory page pointer). These bits were stored (by the
            SST instruction) in the data memory word as follows:

               15 14 13 12  11 10    9  8  7  6  5  4  3  2  1  0
               +--------------------------------------------------+
               |  ARP  |OV|OVM| 1|INTM|             DP            |
               +--------------------------------------------------+


WORDS       1

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  1  0  1  0  0  0  0| 0| data memory address | DIRECT
            +-----------------------------------------------+

            15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  1  0  1  0  0  0  0| 1| see indirect fields | INDIRECT
            +-----------------------------------------------+

CYCLES

            +------------------------------------------------+
            |    Cycle Timings for a Single Instruction      |
            |------------------------------------------------|
            | PI/DI | PI/DE | PE/DI | PE/DE  | PR/DI | PR/DE |
            |-------+-------+-------+--------+-------+-------|
      '20   |   1   |  2+d  |  1+p  | 2+d+p  |   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   1   |  2+d  |  1+p  | 2+d+p  |   1   |  2+d  |
            |------------------------------------------------|
            |    Cycle Timings for a Repeat Instruction      |
            |------------------------------------------------|
      '20   |   n   | 2n+nd |  n+p  | 2n+nd+p|   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   n   | 2n+nd |  n+p  | 2n+nd+p|   n   | 2n+nd |
            +------------------------------------------------+



EXAMPLE     LARP  0
            LST   *,1         The data memory word addressed by the
                              contents of auxiliary register AR0 is loaded
                              into status register ST0, except for the
                              INTM bit. Note that even though a next ARP
                              value is specified, that value is ignored,
                              and even though a new ARP is loaded, the old
                              ARP is not loaded into ARB.


EXAMPLE     LST   >60         (DP = 0)

                BEFORE             AFTER

            dm96 >2404        dm96 >2404
             ST0 >6E00         ST0 >2604
             ST1 >0580         ST1 >0580


EXAMPLE     LARP  AR4         (AR4 = >3FF)
            LST   *-

                BEFORE             AFTER

             AR4  >3FF         AR4  >3FE
          dm1023 >CE06      dm1023 >CE06
             ST0 >FC04         ST0 >CC06
             ST1 >E780         ST1 >E780


EXAMPLE     LARP  AR4         (AR4 = >3FF)
            LST   *-,1

                BEFORE             AFTER

             AR4  >3FF         AR4  >3FE
          dm1023 >EE04      dm1023 >EE04
             ST0 >EE00         ST0 >EE04
             ST1 >F780         ST1 >F780