Click above to get retro games delivered to your door ever month!

      The BIT instruction tests any of the 16 bits of the addressed data
      word. The specified bit is copied into the TC of the status
      register. The bit tested is specified by a bit code in the opcode
      of the instruction. Either the BBZ (branch on TC bit = 0) or BBNZ
      (branch on TC bit = 1) instructions check the bit and allow
      branching to a service routine.

      Bit testing is useful in control applications where a number of
      states or conditions may be latched externally and read into the
      TMS320C2x via the IN instruction. At this point, individual bits can
      be tested and branches taken for the appropriate processing.

      Since the BIT instruction requires the bit code to be specified with
      the instruction, it cannot be placed in a loop to test several
      different bits of a data word or bits determined by prior processing
      for efficient use. The TMS320C2x also has a BITT instruction in
      which the bit code is specified in the T register. Since the T
      register can easily be modified, BITT may be used to test all bits
      of a data word if placed within a loop or to test a bit location
      determined by past processing.

* BIT TEST PROCESSING
*   THIS ROUTINE USES THE BIT INSTRUCTION TO TEST THE CONDITION
*   OF AN EXTERNAL MUX. BIT 4 DETERMINES THE UTILITY OF THE
*   REMAINING DATA. IF ZERO, A COUNTER IS INCREMENTED. IF ONE,
*   ADDITIONAL PROCESSING OCCURS AND THE COUNTER IS CLEARED.
*   THE ROUTINE IS INVOKED WHENEVER A TIMER INTERRUPT OCCURS.
*
TIME  SST   ST0         ; SAVE STATUS REGISTER 0
      LDPK  0
      LARP  AR3
      IN    DAT,PA8     ; READ IN VALUE.
      BIT   DAT,0bh     ; TEST BIT 4.
      BBZ   INCR        ; BRANCH AND INCREMENT IF POSITIVE.
      .
      .
      .
      LARK  AR3,0       ; CLEAR THE COUNTER.
      LST   ST0         ; RELOAD THE STATUS REGISTER.
      EINT              ; ENABLE INTERRUPTS.
      RET               ; RETURN TO INTERRUPTED ROUTINE.
*
INCR  MAR   *+          ; INCREMENT THE COUNTER.
      LST   ST0         ; RELOAD THE STATUS REGISTER.
      EINT              ; ENABLE INTERRUPTS.
      RET               ; RETURN TO INTERRUPTED ROUTINE.

* BIT TEST PROCESSING
*   THIS ROUTINE USES THE BITT INSTRUCTION TO TEST THE CONDITION
*   OF AN EXTERNAL MUX. A BIT IN THE MUX IS SIGNIFICANT ONLY
*   WHEN PRIOR PROCESSING HAS DESIGNATED THE BIT TO BE ACTIVE.
*   INDIVIDUAL PROCESSING WILL TAKE PLACE BASED UPON THE STATE
*   OF THE TESTED BIT. THE BITS ARE TESTED EACH TIME A TIMER
*   INTERRUPT OCCURS.
*
TIME  SST   ST0         ; SAVE STATUS REGISTER ST0
      LDPK  0
      LARP  AR3
      LAR   AR3,BCNT    ; LOAD COUNT OF ACTIVE BITS.
      LRLK  AR3,BTBL    ; LOAD THE BIT TABLE ADDRESS.
      IN    DAT,PA8     ; READ IN VALUE.
      B     LTEST,*-,4
TMLOOP      LT    *+,3  ; LOAD BIT CODE.
      BITT  DAT         ; TEST SPECIFIED BIT.
      BBNZ  LTEST       ; BRANCH IF BIT IS ONE.
      .
      .
      .
LTEST BANZ  TMLOOP,*-,4
      LST   ST0         ; RELOAD THE STATUS REGISTER.
      EINT              ; ENABLE INTERRUPTS.
      RET               ; RETURN TO INTERRUPTED ROUTINE.