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      Interrupts on the TMS320C2x are prioritized and vectored. When an
      interrupt occurs, the corresponding flag is set in the interrupt
      flag register (IFR). If the corresponding bit on the interrupt mask
      register (IMR) is set an interrupts are enabled (INTM = 0), then
      interrupt processing begins.

      When the interrupt vector is loaded into the program counter,
      interrupts are disabled (INTM = 1) and a branch is made to the
      appropriate routine via the branch instruction stored at the
      associated vector location. Since all interrupts are disabled,
      interrupt processing may proceed without further interruption unless
      the interrupt service routine (ISR) re-enables interrupts.

      Unless the interrupt service routines are simple I/O handlers, the
      processing in each ISR generally must assure that the processor
      context is preserved during execution. The context must be saved
      before executing the routine itself and restored when the routine
      is finished. A common routine or routines individualized for each
      interrupt may be used to to secure the context of the processor
      during interrupt processing. Context switching is also useful for
      subroutine calls, especially when extensive use is made of the stack
      or auxiliary registers.

      See "interrupt priority" for example.