Click above to get retro games delivered to your door ever month!

      Scaling the data coming into the accumulator or already in the
      accumulator is useful in signal processing algorithms. This is
      frequently necessary in adaptation or other algorithms that must
      compute and apply correction factors or normalize intermediate
      results. Scaling and normalizing are implemented on the TMS320C2x
      via right and left shifts in the accumulator and shifts of data on
      the incoming path to the accumulator.

      Right and left shifts of the accumulator can be performed using the
      SFL and SFR instructions. SFL performs a logical left shift, SFR
      performs logical or arithmetic right shifts depending on the state
      of the SXM bit in the status register. A one in the SXM bit,
      corresponding to sign-extension enabled, causes an arithmetic shift
      to be performed.

      In addition to the shift instructions, data can be left-shifted 0
      to 15 bits when the accumulator is loaded using the LAC instruction,
      and left-shifted 0, 1, or 4 bits on the TMS32020 and 0 to 7 bits on
      the TMS320C25 when storing from the accumulator using SACH or SACL
      instructions. These shifts can be used for loading numbers into the
      high 16 bits of the accumulator and renormalizing the result of a
      multiply. The incoming left shift of 0 to 15 bits can be supplied
      in the instruction itself or can be taken from the lowest four bits
      of the T register. Left shifts of data fetched from data memory are
      available for loading the accumulator (LAC/LACT), adding to the
      accumulator (ADD/ADDT), and subtracting from the accumulator
      (SUB/SUBT). The contents of the P register may also be shifted prior
      to accumulation.