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Reset register         index 00h  SEQU

Layout  b7-b2      Reserved
        b1     SR  Synchronous reset
        b0     SR  Synchronous reset  (EGA: async reset)

- Sync reset (bit 1 VGA)
        0 : Generate and hold the system in a reset condition.
        1 : Release the reset if bit 0 is in the inactive state.

- Sync reset (bit 0 VGA) (no asynchr. reset in VGA)
        0 : Generate and hold the system in a reset condition.
        1 : Release the reset if bit 1 is in the inactive state.

Note    Controls the state of the sequencer by producing a
        synchronous reset. A synchr. reset preserves memory contents
        and must be used before changing the Clocking mode register to
        avoid loss of memory contents.