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Map mask register      index 02h  SEQU   (a.k.a. Plane mask register)

Layout  b3     EM3  Plane 3 write enable
        b2     EM2  Plane 2 write enable
        b1     EM1  Plane 1 write enable
        b0     EM0  Plane 0 write enable

- Plane enable (bits 3,2,1,0)
        Enables writes to 0-3 planes simultaneously.

        0 : Disable memory plane on CPU write operations
        1 : Enable memory plane on CPU write operations

Note    See WM field of Mode register for different write modes.
        See Bit mask register for bit masking.