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Mode register          index 05h  GRAPH

Layout  b6-b5  SR   Shift register
        b4     OE   Odd/even mode
        b3     RM   Read mode
        b2     TC   (EGA only)
        b1-b0  WM   Write mode

- Shift register (bits 6-5)
        0 : Output the data in a straightforward serial fashion with
            each display plane output on its associated serial output.
            This is the standard VGA format.
        1 : Output the data in a CGA-compatible 320-by-200, four-color
            graphics mode. This is used in display modes 4 and 5.
        2 : Output the data eight bits at a time from the four bit
            planes. This is the format for the VGA mode 13h.
            
- Odd/even mode (bit 4)
        This bit should be the complement of the O/E field in the
        Memory mode register.

        0 : Normal VGA operating mode.
        1 : Controls the VGA, so that even host addresses access even
            display planes (0,2) and odd host addresses access odd
            display planes (1,3).

- Read mode (bit 3)
        0 : Select read mode #0. Data read from the VGA represents
            eight neighboring horizontal pixels in one display plane,
            as specified in the Read map select register.
        1 : Select read mode #1. Data read from the VGA represents
            the result of a comparison made between the eight
            neighboring horizontal pixels from any or all display
            planes with the value in the Color compare register. The
            display planes selected for the comparison are determined
            in the Color don't care register.

- Write mode (bits 1-0)

        b1 b0 Write mode
        0  0  #0   (default) Direct write. See Data rotate, Set/reset,
                   Enable set/reset, Bit mask registers.
        0  1  #1   Used for fast 32-bit mem-to-mem MOVS.
        1  0  #2   Color plane n (0-3) is filled with the value of
                   bit n in the write data (Bit mask register).
        1  1  #3   Uses (rotated) write data ANDed with Bit mask as
                   bit mask. Uses set/reset as if set/reset were
                   enabled for all planes.