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Address register                  ATTRIB

Layout  b5     PAS  Palette address source
        b4-b0  ADR  Attribute address

- Palette address source (bit 5)
        This field is used to control the operation of the dual-ported
        palette RAM. If the host is to have control of the palette
        registers during a load operation, it must reset the PAS field
        to 0 (zero). In order for the VGA display memory to access
        this palette RAM, the PAS field must be set to 1.

- Attribute address (bits 4-0)
        Selects which of the registers of the attribute controller
        will be addressed by the next I/O write cycle.

        Note
        Unlike all the other VGA address/data port pairs, the
        attribute controller has only one port dedicated to it. This
        port resides at host location 03C0h (write). An internal
        hardware flip-flop is used to multiplex this port to load
        either this Address attribute register or one of the Attribute
        registers. When the flip-flop is in the set state, data
        written to this port is directed to whichever Attribute
        register index is loaded into the ADR field of this register.

        The flip-flop is controlled indirectly by the host. When the
        Input status #1 register is read (by an IN instruction), the
        flip-flop is cleared.


        ; Set overscan color
        mov     dx,03DAh        ; Input status #1 reg.
        in      al,dx           ; Dummy input clears flip-flop
        mov     dx,03C0h        ; Attribute controller reg.
        mov     al,11h          ; Index of overscan reg.
        out     dx,al           ; Write address
        ; Flip-flop now set
        mov     al,0eh          ; Data value
        out     dx,al           ; Write data
        ; Flip-flop now clear