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SAR             Shift Arithmetic Right               Flags: O D I T S Z A P C
                                                            * - - - * * ? * *
SAR destination,count

                            +---------------+   +----+
                Sign bit --.|  destination  |--.| CF |
                            +---------------+   +----+

    SAR shifts the bits of the destination operand downward (toward
    the least significant bit) by the number of bit positions
    specified in the second operand (count). As bits are transferred
    out of the right (low-order) end of the destination, bits equal to
    the original sign bit are shifted into the left (high-order) end,
    thereby preserving the sign bit. The carry flag (CF) is set equal
    to the last bit shifted out of the right end.

    The shift is repeated the number of times indicated by the second
    operand, which is either an immediate 8-bit value (max. 1 on the
    8086 processor) or the contents of the CL register. To reduce the
    maximum execution time, the 80186+ uses only the lower 5 bits of
    the count, limiting the count value to 31; the 8086 uses all 8
    bits of count.

    If the count operand is not an immediate 1, the overflow flag (OF)
    is undefined; otherwise SAR resets OF to zero.


    SAR divides a signed integer by a power-of-two. Note that SAR
    rounds toward negative infinity (not the same as IDIV):
        mov     al,-1           mov     ax,-1
        sar     al,1            mov     cl,2
        ; al = -1               idiv    cl
                                ; al = 0


    Opcode      Format
    C0 /7 ib    SAR  r/m8,imm8
    C1 /7 ib    SAR  r/m16,imm8
    C1 /7 ib    SAR  r/m32,imm8
    D0 /7       SAR  r/m8,1
    D1 /7       SAR  r/m16,1
    D1 /7       SAR  r/m32,1
    D2 /7       SAR  r/m8,CL
    D3 /7       SAR  r/m16,CL
    D3 /7       SAR  r/m32,CL


    Length and timing   (Identical for SAR, SHR, SAL, and SHL)
    Operands    Bytes   8088    186     286     386     486     Pentium
    reg, 1       2       2       2       2       3       3       1   PU
    mem, 1    2+d(0,2)  23+EA   15       7       7       4       3   PU
    reg, cl      2       8+4n    5+n    5+n      3       3       4   NP
    mem, cl   2+d(0,2) 28+EA+4n 17+n    8+n      7       4       4   NP
    reg, imm     3       -       5+n    5+n      3       2       1   PU
    mem, imm  3+d(0,2)   -      17+n    8+n      7       4       3   PU*

       * = not pairable if there is a displacement and immediate