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FSTENV          Store FPU environment                Exceptions: None
FNSTENV         Store FPU environment, no wait       C3 C2 C1 C0: ? ? ? ?

FSTENV destination
FNSTENV destination

        Logic   destination . FPU environment

    FSTENV/FNSTENV store the FPU environment at destination (a 14- or
    28-byte memory location) and then mask all FP exceptions. FSTENV
    checks for unmasked FP error conditions before writing the state;
    FNSTENV does not make this check.
    After saving the environment, FSTENV/FNSTENV set all the exception
    masks in the FPU control word, preventing FP errors from
    interrupting an exception handler.
    

    Code
    segment Operation           Req'd size of   Offset into dest. of
    size    mode                destination     CW   SW   Tag word
    16-bit  Real mode/V86 mode  14 bytes        0    2    4
    16-bit  Protected mode      14 bytes        0    2    4
    32-bit  Real mode           28 bytes        0    4    8
    32-bit  Protected mode      28 bytes        0    4    8

    Note: For use in FPU error handlers, an error block is included in
          the environment. Refer to Intel's documentation for details.


        Example
        pushf
        cli             ; No interrupts
        fstenv [bp-14]  ; Wait until not busy, then store env.
        fwait           ; Wait for instruction to finish
        popf            ; Restore flags
        ; ...


    Opcode      Format
    9B D9 /6    FSTENV m14byte  ; 16-bit code segment
    9B D9 /6    FSTENV m28byte  ; 32-bit code segment
    D9 /6       FNSTENV m14byte ; 16-bit code segment
    D9 /6       FNSTENV m28byte ; 32-bit code segment


    Timing
    Variations/
    operand       8087         287        387      486     Pentium
    fstenv   mem  (40-50)+EA    40-50     103-104   67/56    48-50   NP
    fstenvw  mem                          103-104   67/56    48-50   NP
    fstenvd  mem                          103-104   67/56    48-50   NP
    fnstenv  mem  (40-50)+EA    40-50     103-104   67/56    48-50   NP
    fnstenvw mem                          103-104   67/56    48-50   NP
    fnstenvd mem                          103-104   67/56    48-50   NP

                Cycles for real mode/protected mode
                The wait version may take additional cycles

See Also: FLDENV FSAVE FPU registers

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